Luca Benini

[intermediate/advanced] Open Hardware Platforms for Edge Machine Learning

Summary

The course will look at designing RISC-V procesors and accelerators targeting Machine Learning applications. Techniques for instruction-set-architecture (ISA) extension will be presented, focusing on energy-efficient micro-architecture design. The lecture will also delve in accelerator design, and on integrating heterogeneous computing engines for achieving higher performance and efficiency, while retaining flexibility. Several examples will be provided from the open-source PULP (pulp-platform.org) Systems-on-Chip.

Syllabus

• Part 1: Specializing Processors for ML: RISC-V and its ISA, Micro-architecture of a RISC-V MCU, Extending the ISA for ML, Designing efficient RISC-V cores for ML workload.
• Part 2: From Single to Multi-Core Heterogeneous SoCs for ML: Parallel ultra-low Power (PULP) architecture, ML acceleration engines, Memory hierarchy and IO optimization for ML workloads.

References

General Surveys of the topic: https://arxiv.org/abs/2310.09145, https://arxiv.org/abs/2306.15552

Dedicated resources: https://pulp-platform.org/

Pre-requisites

Basic computer architecture (CPU, ISA, memory hierarchy). Basic digital hardware design (digital logic, elementary computer arithmetic, power consumption of digital circuits).

Short bio

Luca Benini holds the Chair of Digital Circuits and Systems at ETHZ and is Full Professor at the Università di Bologna. He received a PhD from Stanford University. Dr. Benini’s research interests are in energy-​efficient parallel computing systems, smart sensing micro-​systems and machine learning hardware. He is a Fellow of the IEEE, of the ACM and a member of Academia Europaea. He is the recipient of the 2016 IEEE CAS Mac Van Valkenburg Award, the 2020 EDAA Achievement Award, the 2020 ACM/IEEE A. Richard Newton Award and the 2023 IEEE CS E.J. McCluskey Award.